Books Written/Edited

  • Jin He, Haijun Lou, Lining Zhang and Mansun Chan, Silicon-Based Nanowire MOSFETs: From Process and Device Physics to Simulation and Modeling, Ch. 15 in Nanowires – Implementations and Applications, edited by Abbass Hashim, Intech, 2011 

  • M. Chan, Stacked CMOS Technology, Ch. 3 in Wafer Level 3-D ICs Process Technology, edited by C. S. Tan, R. J. Gutmann, and R. L. Reif, Springer, 2008 

  • Richard S. Muller, Theodore I. Kamins, Mansun Chan, Device Electronics for Integrated Circuits, 3rd edition, John Wiley, 2002 

  • Williams En, Erin C. Jones, James C. Sturm, Mansun Chan, Sandip Tiwari, Masataka Hirose (editors), “Materials Issues in Novel Si-Based Technology”, Materials Research Society, Symposium Proceedings, Vol. 686 

US Patents

  • T. Y. Man, P. K. T. Mok and M. Chan, " Frequency-Hopping Pulse-Width Modulator for Switching Regulators", US Patent 8,760,141 B2, June 24, 2014 
     

  • T. Y. Man, C. Y. Leung, K. N. Leung, P. K. T. Mok and M. Chan, "Single-Transistor-Control Low-Dropout Regulator", US Patent RE42,335 E, May 10, 2011. 
     
  • Mansun Chan, Chen Xu, and Wing Hung Ki, “Ultra Low Voltage CMOS Image Sensor Architecture”, US Patent 7,897,901 B2, March 1, 2011 
     
  • Mansun Chan, Chen Xu, and Wing Hung Ki, “Ultra Low Voltage CMOS Image Sensor Architecture”, US Patent 7,858,912 B2, December 28, 2010 
     
  • Mansun Chan, Jiong Li, Yijin Wang, and Zuhong Lu, “Integrated Circuit Optical Detector for Biological Detection”, US Patent 7,585,664, September 8, 2009 
     
  • P. C.-H. Chan, M. Chan, X. Wu, and S. Zhang, “Complementary Metal-Oxide-Semiconductor Transistor Structure for High Density & High Performance Integrated Circuits”, US Patent 7,545,008, June 9, 2009 
     
  • T. Y. Man, C. Y. Leung, K. N. Leung, P. K. T. Mok and M. Chan, "Single-Transistor-Control Low-Dropout Regulator", US Patent 7,285,942, October 23, 2007. 
     
  • M. Chan, C. Xu, and W.-H. Ki, "Ultra Low Voltage CMOS Image Sensor Architecture", US Patent 7,005,626, February 28th, 2006 
     
  • M. Chan, Philip Ching Ho Chan, Xusheng Wu and Chuguang Feng, “Method for Patterning Fins and Gates in a FinFET Device Using Trimmed Hard-Mask Capped with Imaging Layer”, 20060177977, August, 2006 
     
  • M. Chan, P. C.-H. Chan, and V. W.-C. Chan, "3D Integrated Circuit Fabrication on Multi-Layer LPSOI", US Patent 6,727,517, April 27th, 2004 
     
  • M. Chan, H.-J. Wann, P. Ko, and C. Hu, "Silicon-On-Insulator Transistors Having Improved Current Characteristics and Reduced Electrostatic Discharge Susceptibility (Part 4)", US Patent 6,300,649, October 17th, 2001 
     
  • M. Chan, H.-J. Wann, P. Ko, and C. Hu, "Silicon-On-Insulator Transistors Having Improved Current Characteristics and Reduced Electrostatic Discharge Susceptibility (Part 3)", US Patent 6,121,077, September 19th, 2000 
     
  • M. Chan, H.-J. Wann, P. Ko, and C. Hu, "Silicon-On-Insulator Transistors Having Improved Current Characteristics and Reduced Electrostatic Discharge Susceptibility (Part 2)", US Patent 5,982,003, November 9th, 1999 
     
  • M. Chan, H.-J. Wann, P. Ko, and C. Hu, "Silicon-On-Insulator Transistors Having Improved Current Characteristics and Reduced Electrostatic Discharge Susceptibility (Part 1)", US Patent 5,489,792, February 6th, 1996. 

Manuals Written

  • X. Xi, K. M. Cao, H. Wan, M. Chan, C. Hu, “BSIM4.2.1 MOSFET Model – User’s Manual”, November 2002, University of California at Berkeley 

  • Samuel K. H. Fung, D. Sinitsky, S. Tang, R. Tu, M. Chan, P.K. Ko, and C. Hu, "BSIM3SOI v1.0 Manual", November 1997, University of California at Berkeley 

  • Y.-H. Cheng, M. Chan, K. Chen, J. Chen, J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, P. K. Ko and C. Hu, "BSIM3 version 3.0 Manual", July, 1995, University of California at Berkeley 

  • J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko and C. Hu, "BSIM3 Manual (version 2.0)", March, 1994, University of California at Berkeley 

Forums and Workshop

  • M. Chan, "Multi-Gate MOSFET Based Non-volatile Memory Design", The 11th WIMNACT Workshop and IEEE EDS Distinguished Mini-colloquium on Nanometer CMOS Technology, July 4, 2006, Singapore 

  • M. Chan, "3-D Multi-layer CMOS Integrated Circuits", Workshop on Technology of Si-Based Nano-devices, February 24, 2006, Singapore 

  • M. Chan, "3-D Multi-layer Integrated Circuit Technologies for Interconnect Reduction", The 8th WIMNACT Workshop and IEEE EDS Distinguished Mini-colloquium on Nanometer CMOS Technology, July 2, 2005, Singapore 

  • M. Chan, "Nano-Electronic: The Driving Force of the Information Revolution", August 7, 2004, General Lecture on Nano-Technology, Hong Kong Science Museum 

  • M. Chan, "Introduction to Nano-electronic Technology Options: From Traditional to Futuristic Device Structures", Lecture to the Hong Kong Institution of Engineers, July 12, 2004, Hong Kong Productivity Council 

  • M. Chan, "Nano-CMOS Technology Options: From Traditional to Futuristic Device Structures", The 3rd WIMNACT Workshop and IEEE EDS Distinguished Mini-colloquium on Nanometer CMOS Technology, October 15, 2003, Singapore 

  • M. Chan and Y. Taur, "Compact Modeling of Double-Gate MOSFETs", Semiconductor Research Corporation (SRC) Review, June 18, 2003, USA 

  • M. Chan, "The Challenge from Industry on Higher Education in the IT Age", 1999 Hong Kong Forum on The Use of Information Technology For Education, 6 February 1999, Hong Kong Polytechnic University 

  • M. Chan, "What to Expect at an American University", Pre-departure Orientation for US Study, July 7, 2000, Hong Kong Convention & Exhibition Center