i-MOS–interactive Modeling and Online Simulation is a web-based free-to-use platform accommodating both device model developers and circuit designers by enabling circuit design based on emerging and conventional technologies. Model implementation in i-MOS gives model developers a chance to promote and evaluate their models based on user’s feedback. The circuit designers also get a chance to try out recent models before they are released by EDA vendors. The platform aims to provide a standard interface to the model users where they can evaluate and compare models easily based on standard benchmark tests.
The platform is currently in its development phase. In its current state, the platform can be used to:
- Produce the output characteristics of the models in the device library, full list of device library can be accessed in the model page.
- Do an online simulation of simple circuits based on the device models in the library.
- Import, export and save custom user-defined parameters for the different device models.
- Download and save output characteristics in text form.
- Compare device output characteristics of the different devices.
In future, the i-MOS platform will be able to do first principle simulations device parameter extractions to be used in device modeling and subsequent circuits. Click to visit the i-MOS website.
Carbon Based Electronics
Carbon based 1D and 2D materials has spurred great interest in the electronics community due to their unique physical properties and interesting physics. To satisfy our curiosity, the group is also working on new concepts related to carbon nanotube and graphene with special focus on:
- Employing carbon nanotube for future interconnect technology as the scaling trend enters the sub-20nm regime where increased resistivity and electro-migration of copper becomes serious. The project is to study the integration of CNT as via filling material into the mainstream CMOS technology.
- Modeling aligned Carbon Nanotube array based FETs in the presence of the additional CNT density variations, compared to the conventional planar technology. As CNTFET emerges as a mature post-CMOS technology, the aim is to realistically predict and project the CNT density requirements to challenge the conventional silicon transistor technology.
- Using graphene as the contact electrode for FET and TFT applications and exploring the unique physics of a 2D-3D contact.
The collective functionality of an RF system achieved by the interaction between electronics and electromagnetic system. Our research focuses on the design and implementation of on-chip electromagnetic components. We create modeling and simulation algorithms to design on-chip components, including inductors, transformers, and matching networks. Application of these simulation algorithms expands from high frequency, e.g. near-field wireless power transmission, to millimeter wave communication technologies.
Embedded Memory Circuits
The group focuses on circuit techniques for the design of power efficient cache memories. Each level of the cache hierarchy, from the register file that lies within the processor core to the shared level-3 cache, presents a unique set of design challenges that need to be addressed with a delicate compromise between speed, size, and power. Design solutions are rigorously simulated using device models in TCAD and foundry PDKs in Cadence Design Suite. Silicon validation is deemed essential in order to claim competitive advantage.
The organic thin film transistors (OTFT) is lucrative for printed and flexible electronic systems. Our group works towards understanding the fundaments of OTFT which includes the carrier transport through organic materials, organic material to metal contacts and suitable device structures for large scale integration.